VHDL Tutorial 18: Design a T flip-flop (with enable and an active high reset input) using VHDL
VHDL code for D Flip Flop - FPGA4student.com
ECE 545 Lecture 7 Behavioral Modeling of Sequential-Circuit Building Blocks Mixing Design Styles Modeling of Circuits with a Regular Structure. - ppt download
synchronous and Asynchronous reset VHDL
Asynchronous reset synchronization and distribution – Special cases - Embedded.com
Sequential-Circuit Building Blocks) - ppt download